Job Title: FPGA Engineer
Work Location: Cedar Rapids, IA (5 Days Onsite)
Position Type: 12+ Months Contract
What You'll Be Doing:
Requirements capture, ASIC / FPGA digital architecture and design using RTL, timing closure, verification, and system integration
Recommend new tools and practices for continuous improvement in the group's ASIC / FPGA design flow
Contribute to engineering estimates for new program pursuits.
May provide technical leadership for project design teams by breaking down work, planning activities, and reporting status
What We Are Looking For:
RTL coding and simulation in VHDL/Veriog
Digital circuit architecture, design, resource tradeoffs, timing analysis and timing closure
Proficiency using ASIC and/or FPGA simulation and synthesis tools (e.g. Modelsim, Synplify, Quartus, Vivado, or other FPGA-specific tools)
Git, Subversion
Experience with Unix, scripting, C/C++, and/or Perl
Preferred Skills:
Familiarity with best practice chip-level verification techniques and languages (e.g. constrained random, functional coverage, SystemVerilog)
ASIC / FPGA lab validation with advanced lab equipment
Design for Test (DFT) and manufacturability issues
Experience with Unix, scripting, C/C++, and/or Perl
Any special or skills related notes: Ability to work with minimal supervision, team with engineers of a variety of skills and backgrounds, and matrix into projects with aggressive schedules and frequent milestones Strong oral and written communication skills with the ability to document and present one's work and status
Education: Bachelor's / Masters
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